The present invention relates generally to packet switching systems, and more specifically to a fast packet switching system for ISDN (Integrated Services Digital Network).
Research effort has currently been focused on fast packet switching systems for transporting and switching all classes of information by segmenting signals into small packets and transporting them using simplified protocols. An architecture of such a fast packet switching system is described in a paper "A shared buffer memory switch for an ATM exchange", H. Kuwahara et al, (CH2655-9/89/0000-0118) 1989, IEEE. According to this technique, incoming packets are bit-sliced by a serial-to-parallel converters into packet segments for coupling to respective connection oriented sub-switching systems, and sequenced again by parallel-to-serial converters into the original packet at the output port. If the incoming packet has an L-bit length, it can be bit sliced to a maximum of L packet segments, allowing the sub-switching systems to operate at a speed 1/L of the speed of serial processing.
The switching speed of the prior art packet switching systems is given by the relation N.times.V/K, where V is the line transmission speed, N the number of input ports, and K the number of packet segments into which each packet is bit-sliced. For a given switching speed, the line speed and the number of input ports can be increased by increasing the K value whose maximum value is equal to the bit length L. Typical values are N=32, V=4.8 Gbps, and L=K=53 bytes for a switching speed of 362 Mbps. However, this value is still too high for implementing packet switching systems.